Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance ...

Placement of multiple dies on an MCM or high-performance VLSI substrate is a non-trivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. Unfortunately, the exact physical attributes of a design are not known in the placement step until the entire design process is carried out. When the performance issues are considered, crossta...

Advanced Gate Technologies for Deep-Submicron CMOSFETs

Important features of a deep-submicron MOSFET drain current model capable of supporting both digital and analog circuit simulations are described. Formulation of the commonly used mobility and velocity saturation models have to be revised to account for the influnce of the higher clecttic field in deep-submicron devices. For analog circuit simulations, output resistance modeling and smooth tran...

0272-1732/99/$10.00  1999 IEEE Deep-submicron technology allows billions of transistors on a single die, potentially running at gigahertz frequencies. According to Semiconductor Industry Association (SIA) projections, the number of transistors per chip and the local clock frequencies for high-performance microprocessors will continue to grow exponentially in the near future, as Figure 1 (on th...

Standby Power Management Architecture for Deep-Submicron Systems

Page On the Synthesis-Oriented characteristics of high performance, deep-submicron CMOS VLSI cell libraries.

A-Tree is a rectilinear Steiner tree in which every sink is connected to a driver by a shortest length path, while simultaneously minimizing total wire length. This paper presents a polynomial approximation algorithm for the generalized version of A-Tree problem with upper-bounded delays along each path from the driver to the sinks and with restrictions on the number of Steiner nodes. We refer ...